Enhancing High-Volume DRAM Device Manufacturing with TEM Metrology and Characterization

Dynamic random access memory (DRAM) plays a crucial role in computing devices, providing fast access to essential data and allowing them to operate at peak performance. For DRAM manufacturers, scaling is important as it enables lower cost per unit area by enabling reductions in DRAM cell size. However, as DRAM cells scale down to a smaller size, enabling scalable memory systems without sacrificing reliability can be challenging.

DRAM device manufacturing and metrology challenges

Each individual cell within a DRAM chip contains a transistor and a capacitor that collectively constitute the fundamental unit of data storage. The manufacturing process of DRAM cells is highly intricate and involves various critical steps, including ISO area etch, buried wordlines, bit line and contact, storage node contact, capacitor etch and mesh spacer, and capacitor plate formation as shown in Figure 1.

Each of these process steps requires precise control of key metrology targets at the nanometer scale. However, the complex three-dimensional (3D) nature of DRAM cells poses challenges for existing fab metrology and inspection solutions when it comes to accurately measuring and characterizing deeply buried features.

DRAM device fabrication process and challenges.

Figure 1. The DRAM device manufacturing process and challenges impacting each step.

For example, during the ISO area step, when the lateral critical dimension (CD) of the transistor structure is shrinking towards 10 nm, accurate measurement of the vertical etch profile and its uniformity becomes challenging for conventional two-dimensional, top-down metrology solutions. By utilizing focused ion beam (FIB) sample preparation, DRAM device manufacturers can acquire 3D information about the intricate cell structure. Following this with high-resolution imaging techniques like scanning electron microscopy (SEM) and transmission electron microscopy (TEM), precise measurements of the DRAM cell structure with nanometer- or sub-nanometer-resolution and high precision are enabled.

Increasing DRAM cell densities

As demand for lower-cost, higher-density DRAM increases, the drive to increase cell density in DRAM devices necessitates the incorporation of capacitors with closely packed patterning (Figure 2). However, as unit cells approach their scaling limit due to continuous CD shrinking, novel approaches are being proposed to preserve the capacitance of DRAM capacitors and optimize the functionality of high-dielectric materials. These approaches primarily focus on the development of ultra-thin dielectric materials with a higher dielectric constant (high-k) and low-leakage currents. Consequently, the increased possibility of process variation fabricating those thin film stacks has caused a narrower process window at each step. As a result, accurately measuring capacitor CDs and conducting elemental analysis of the DRAM cells are increasingly crucial and can be challenging.

Scanning transmission electron microscopy of DRAM device

Figure 2. Scanning transmission electron microscopy image showing closely packed DRAM capacitors with a concentric layer structure.

To meet these evolving needs, high-volume and high-precision TEM analysis has emerged as the new standard in the semiconductor industry. For example, characterization of DRAM capacitors, particularly the elemental distribution of the thin film stack containing high-k materials, poses significant challenges due to their sensitivity to electron beams. Prolonged exposure to electron beams can result in sample beam damage and artifacts in the results that prevent accurate TEM metrology and analysis.

Innovative DRAM device solutions

However, these challenges are now being overcome with the introduction of a new-generation energy dispersive X-ray spectroscopy (EDS) detection system. This advanced system offers at least 2× greater collection efficiency compared to its predecessors, enabling the collection of high volumes of EDS analysis data on DRAM capacitor samples without causing any damage. The analysis can be efficiently conducted on the state-of-the-art Thermo Scientific Metrios 6 Scanning Transmission Electron Microscope (STEM), which offers a fully automated TEM imaging, metrology, and characterization workflow.

Figure 3 demonstrates the advantages of the EDS analysis mapping data collected using the ultra-fast Ultra-X detector in comparison to its predecessor, the Dual-X detector. The Ultra-X detection system enables efficient characterization of the beam-sensitive DRAM capacitor structure, even when using the same electron dose.

Figure 3. The clear visualization of the delicate cell structure is demonstrated, showcasing the presence of ~1 nm aluminum-containing layers (indicated by arrows).

Moreover, EDS metrology is frequently employed as a supplementary technique to assess elemental distribution ^[1], particularly in cases where it is challenging to measure under imaging mode (Figure 4). This high-efficiency EDS analysis system expands the possibilities of accurately measuring intricate DRAM capacitor structures.

EDS metrology on Al, Ti, and Zr in DRAM device.

Figure 4. EDS metrology on Al, Ti, and Zr in DRAM capacitors.

For high-volume DRAM device manufacturing, these advancements in TEM metrology and EDS characterization techniques offer significant benefits. Not only do they aid in characterizing the high-k, thin deposition process for capacitor manufacturing, they also provide a solution for measuring metrology targets with highly localized information. This level of precision and accuracy is crucial for improving DRAM reliability and manufacturing processes.

Curious to learn more? If you are interested in understanding how the Ultra-X detection system and the Metrios 6 (S)TEM achieve these remarkable results, please watch our on-demand webinar on Automated STEM-EDS Metrology and Characterization of DRAM Capacitors. Discover the cutting-edge technologies that are revolutionizing the semiconductor industry and empowering high-volume DRAM device manufacturing.

[1]. A. Tilson and M. Strauss, “STEM/EDS Metrology and Statistical Analysis of 3D NAND Devices”, IPFA 2018.