Chips are made using a precise manufacturing process with constant testing. Silicon wafers are constructed layer by layer using repeated processing steps that involve gases, chemicals, solvents and the use of ultraviolet light. The processes include growth/deposition of epitaxial layers and dielectric films, patterning (lithography and etch), implantation (doping) and diffusion, and deposition of interconnection metals (aluminum, copper). Each layer is patterned into extremely fine structures with micron or even nanometer dimensions to develop an integrated circuit (IC) that creates millions to billions of interconnected transistors. When completed, a single wafer will contain hundreds of identical dies (chips) that must pass rigorous testing and are then cut from the wafer. Each chip is then mounted onto a metal or plastic package. The mounted chip undergoes final testing and then is ready to be assembled into final products.

On this page

Quality control challenges in semiconductor wafer fabrication

Manufacturing StepQuality control challenges
Wafer / substrate preparation (wafer cleaning)Ensure wafer cleanliness, absence of silicon crystal defects and impurities. Wet cleaning requires ultrapure chemicals, ultrapure water (dilution, rinsing), and ultrapure organic solvents (e.g. IPA, used for Marangoni wafer drying).
Ion implantationIon dose and implant profiles need to be well controlled, crystal damage and amorphization has to be minimized, such as by using an optimized Temperature Anneal step after ion implant. Ion source gases (AsH3, PH3, BF3, B2H6 etc.) need to be controlled for impurities to avoid spurious co-implants.
Thermal processesUsed for anneals (after ion implant, Cu deposition) or growth of layers such as silicon oxide or silicides. Reactor cleanliness and purity of gases are important to avoid impurities in the grown layers or unwanted reactions with materials present on the wafer.
Film depositionUsed for deposition of thin, conformal dielectric, or metallic films. Dielectric films are mostly formed using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD) processes.

Dielectric films have to be well controlled in terms of thickness, composition and thermo-mechanical properties.
  • Chemical precursors (gases, vapors, liquids) need to be clean and have high purity to guarantee the quality of the deposited films.
  • Metallic films are formed by LPCVD/ Sputtering/ALD (Tungsten, seed and barrier layers such as Ta and TaN) or Electrochemical deposition (plating of Copper).
  • Barrier, contact, or seed films are very thin and need to be of high purity and of a well-controlled chemical composition to ensure the correct physical and electrical properties.
  • Plating baths for Copper ECD need to be of well controlled composition and free of contaminants to ensure a metal deposition with the correct characteristics. Copper thickness, crystal orientation and grain size need to be optimized to ensure the correct conductance and to minimize degradation due to electromigration.
CMP (Chemical Mechanical Polishing)To minimize topography, CMP is used to remove materials and to planarize the wafer surface. CMP is a mechanical/chemical process that needs to be well controlled to obtain the desired results and to avoid wafer damage and contamination. The used chemical slurries need to be well controlled in terms of particle size distribution and chemical composition.
PhotolithographyUV optical lithography is used to pattern the device structures on the wafer. Resist is deposited on the wafers and then the resist is illuminated through a mask in a scanner and subsequently developed in a developer track. The control of the lithography steps is extremely critical as the smallest dimensions of the active devices are defined in these steps. CD, resist profiles, line edge roughness etc. need to be measured. To ensure a reliable litho process the clean room air also needs to be well controlled. The smallest amount of refractory hydrocarbon contamination can be detrimental for the litho process (lens contamination), but also traces of acids, bases and resist solvents such as PGMEA, ethyl lactate in the CR air can have negative impacts by creating defects on the wafers.
Wet or dry etchingEtching patterns films and layers in the device structures according to the layout of the resist or hard masks that are created on the wafers in the preceding photolithography steps. The etch process needs to be controlled in terms of etch speed, anisotropy, and selectivity as these parameters will determine the final shape and dimensions of the patterned structures (contacts, vias, lines, etc.). As the etch processes are based on a large variety of reactive and inert gases (or chemicals for wet etch steps), the purity control of these gases and liquids are very important.

Solutions for semiconductor wafer fab analysis

Thermo Fisher Scientific provides many solutions to physical and chemical testing in the semiconductor industry.

Learn more

CMD SchemaApp code