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Semiconductor device packaging analysis
Performance, power efficiency, area, and cost are driving new integration approaches and innovations in advanced semiconductor device packaging. Integration schemes that extend into the Z-dimension provide greater performance and flexibility to meet the needs of application-specific use cases.
As advanced packaging techniques evolve, failure analysis challenges increase, requiring fast, precise, and accurate time-to-data.
Engineering the next generation of advanced semiconductor packaging
Advanced packaging strives to improve performance, power efficiency and device reliability while continuing to reduce production costs and increase yield. 3D-IC, 2.5D, wafer level packaging, and other advanced packaging schemes are becoming increasingly more complex and 3-dimensional. This can lead to a number of performance and reliability challenges, including:
- Die level defects
- Substrate imperfections
- Through-silicon via (TSV) formation problems
- Wafer thinning
- Bonding and bump pitch issues
These require high-confidence fault isolation, nanoscale analysis, and repeatable workflows to accelerate process improvements and time-to-market.
Advanced semiconductor packaging failure analysis
Faults localization in advanced packaging devices is particularly challenging as many factors can result in device failures. These include chip integration, material mismatches, chip-package interactions, thermo-mechanical deformation, and bonding processes.
This places a greater premium on precise fault localization and accurate root cause analysis solutions.
Thermo Fisher Scientific offers a unique and comprehensive set of workflows to meet the failure analysis and defect characterization needs of advanced semiconductor packaging.
Example semiconductor packaging analysis workflows
1. Advanced packaging assembly failure isolation and analysis workflow:
2. In-die failure analysis workflow:
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Thermal Fault Isolation
Uneven distribution of local power dissipation can cause large, localized increases in temperature, leading to device failure. We offer unique solutions for thermal fault isolation with high-sensitivity lock-in infrared thermography (LIT).
Sample Preparation of Semiconductor Devices
Thermo Scientific DualBeam systems provide accurate TEM sample preparation for atomic-scale analysis of semiconductor devices. Automation and advanced machine learning technologies produce high-quality samples, at the correct location, and a low cost per sample.
Semiconductor Analysis and Imaging
Thermo Fisher Scientific offers scanning electron microscopes for every function of a semiconductor lab, from general imaging tasks to advanced failure analysis techniques requiring precise voltage-contrast measurements.
Device Delayering
Shrinking feature size, along with advanced design and architecture, results in increasingly challenging failure analysis for semiconductors. Damage-free delayering of devices is a critical technique for the detection of buried electrical faults and failures.
Nanoprobing
As device complexity increases, so does the number of places defects have to hide. Nanoprobing provides the precise localization of electrical faults, which is critical for an effective transmission electron microscopy failure analysis workflow.
Thermal Fault Isolation
Uneven distribution of local power dissipation can cause large, localized increases in temperature, leading to device failure. We offer unique solutions for thermal fault isolation with high-sensitivity lock-in infrared thermography (LIT).
Sample Preparation of Semiconductor Devices
Thermo Scientific DualBeam systems provide accurate TEM sample preparation for atomic-scale analysis of semiconductor devices. Automation and advanced machine learning technologies produce high-quality samples, at the correct location, and a low cost per sample.
Semiconductor Analysis and Imaging
Thermo Fisher Scientific offers scanning electron microscopes for every function of a semiconductor lab, from general imaging tasks to advanced failure analysis techniques requiring precise voltage-contrast measurements.
Device Delayering
Shrinking feature size, along with advanced design and architecture, results in increasingly challenging failure analysis for semiconductors. Damage-free delayering of devices is a critical technique for the detection of buried electrical faults and failures.
Nanoprobing
As device complexity increases, so does the number of places defects have to hide. Nanoprobing provides the precise localization of electrical faults, which is critical for an effective transmission electron microscopy failure analysis workflow.
Semiconductor Materials and Device Characterization
As semiconductor devices shrink and become more complex, new designs and structures are needed. High-productivity 3D analysis workflows can shorten device development time, maximize yield, and ensure that devices meet the future needs of the industry.
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Electron microscopy services for
semiconductors
To ensure optimal system performance, we provide you access to a world-class network of field service experts, technical support, and certified spare parts.
